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Experimenting With Analog Delay

Article from Polyphony, July/August 1978


I guess it's not unusual that analog delay lines and time domain processing have found such a comfortable home in today's electronic influenced music. After all, music is an artform which is 100% dependent on one single dimension for its realization — time. Musical works are performed in time. Even the tones from instruments are smaller recurring time periods, and musical harmony or intervals are ratios of time periods (frequencies). Looking at the situation from this standpoint, one begins to wonder how we lived without delay lines for so long. Up to now the delay lines have been used primarily to process audio rather than generate audio, so we haven't even begun to realize the potential of these devices. Perhaps one reason for the heretofore obscurity of these devices in the homebrew artist's repertoire is the relative high cost of the ICs themselves, probably due to (or at least compounded by) the lack of availability on the hobbyist or consumer components market. PAIA's recently announced release of the EK-5 Delay Line experimenter's kit should help provide the basic tools — and inspiration required to get these nifty devices into the hands of all you mad wire freaks, so let's discuss a bit about how the Reticon SAD-1024 works and some basic applications to get you started.

ABOUT THE SAD-1024



Figure 1
Pin configuration. Note: Unused outputs should be connected to Vdd; all other unused pins should be connected to GND, Pin 1, including those marked N.C.

The SAD-1024 represents a third generation of bucket brigade analog delay line technology. As a result of the design and the use of N-channel silicon gate fabrication technology, the SAD-1024 provides operational specs and simplicity far surpassing most of the comparable delay lines. As a direct result of the use of N-channel technology, these delay lines feature: single supply operation, higher speed, better frequency response, better linearity, greater dynamic range, lower harmonic distortion, etc. With proper termination, the SAD-1024 can achieve unity gain, eliminating the need for gain restoration stages (and thus, added noise) after each delay line. Power requirements are greatly simplified since the SAD-1024 requires only a single supply. Many of the P-channel delay lines require three or four supply and bias lines. While specified to operate at 15 volts, the SAD-1024 can operate on supply voltages as low as 3.5 volts, allowing easy application in battery powered equipment, or direct control from 5 volt logic supplies and clock sources.

The SAD-1024 contains two independent 512 stage analog delay lines. The pinouts of the IC are shown in figure 1. Figure 2 shows an equivalent circuit schematic for one of the two delay lines in the IC. Figure 3 shows the schematic of one half of the PAIA EK-5 circuit configuration. Armed with these visual aids, let's see how the chip works.

Figure 2
Equivalent circuit diagram of either 512-stage section of the SAD-1024.


Figure 3
NOTE: Pin numbers in parenthesis indicate pinouts for second half of ICs. Component designators identical for each half of circuitry.
(Click image for higher resolution version)


Most of you, as synthesists, will be familiar with the concept of "sample and hold". This is used quite extensively in synthesizer keyboards, and basically operates as follows. An applied input voltage is always moving, or can be varied. At some point in time, the sample-hold circuit can be triggered to sense what the voltage is, and this voltage is stored on a capacitor until the next trigger pulse causes the stored voltage to change to a new level. For the most part, this is how an analog delay line works also. The primary difference is that there are 512 sample and holds all in a row, and on each "trigger" the stored voltage is passed from one holding capacitor to the next until the voltage once again appears at the output. The analogy most often used to explain the analog delay lines is a bucket brigade. Most people have heard of or seen firefighters using a bucket brigade to pass water from person to person to get it to the fire. Well, think of the line of firemen as the analog delay line, and think of the buckets of water as the charges stored on the capacitors in the delay line. This is where these devices picked up the nickname of Bucket Brigade Devices (BBD).

On a more technical level, let's look at the internal schematic as shown in figure 2. For the sake of argument let's say we are feeding the clocking inputs with a 100 kHz. square wave. The two clock lines, Ø1 and Ø2 require complementary signals (square waves 180° out of phase) with minimal ringing or undershoot. That is why you will so often see a CD4013 flip flop driving a delay line. The CMOS flip flop is fast, creating minimal undershoot, and automatically generates complementary outputs. To initially get a signal into the delay line, Ø1 must be at a high logic level, near +v. This turns on the first input transistor (N-channel MOS) to connect the A input to the first storage capacitor, Cs. Concurrently, the LOW logic level on the Ø2 clock line keeps the transistor switch of the first stage (immediately above the "1" designation in figure 2) shut off. At the next clock transition, the instantaneous voltage at the input terminal is "frozen" on Cs as Ø1 drops low (near ground) and shuts off the input transistor switch. However, note that Ø2 is now high, thus enabling the #1 transistor and allowing a path for the charge on Cs to discharge into the first capacitor, in stage 1. During this half period of clocking, there is readjustment of charge from Cs to cell 1. During the next clock half cycle, Ø1 is again enabled to take another sample from the input, and this time also allows the charge in cell 1 to pass to cell 2. In this way, each sample is passed along until it appears at output A with a delay of 512 clock half periods. With the 100 kHz. clock frequency we are using as an example, the output will appear at output A 2. 56 milliseconds after it was input. Note that only one sample is taken at the input per clock cycle, and the output appears at "A" only while Ø1 is high. When the Ø1 falls, the "A" output will fall to its normal low output. An identical output signal will now appear at output A'. At the 510th cell, the signal is split and sent to two outputs, one line having an extra cell to provide an extra half clock cycle of delay. Thus, through summation of the two outputs, a continuous stair-step approximation of the original input is obtained. Without the second output the output would have a great deal of high frequency clock content, as the analog signal information would be presented on only the top pedestals of every other clock half cycle as shown in figure 4. As seen from the timing graph of figure 4, the summed outputs produce a more constant audio signal with only minor, short duration clock switching glitches which are easily removed even with crude passive filtering.

Figure 4


An important concept involved in the use of analog delay lines is sampling theory. Specifically, how many samples are required to accurately reproduce an audio signal? Of course, the more samples taken of a waveform, the more refined the "stair-step" approximation at the output of the delay line will be. However, in an attempt to get longer delay times out of the analog delay line, the designer runs head-on into sampling problems. Good reconstruction of waveform occurs with 10 samples per cycle or more, but as the clocking frequency falls towards 2 or 3 times the highest frequency to be sampled, the delay system approaches what is called "critical sampling". Theoretically, a sine wave of specified frequency can be reproduced with only two samples per cycle. This, of course, is a theoretical limit, so we should try to maintain a clock frequency which is at least 3 or 4 times the highest frequency to be processed. In an audio system requiring bandpass to 15 kHz., this would then imply a minimum clock frequency at Ø1 and Ø2 of around 50 kHz. Recalling that most delay systems will use a flipflop to provide bi-phase clock signals, and remembering that this flip-flop circuit configuration generates a frequency division of 2, this means that the system clock should have a minimum of around 100 kHz. In a mathematical sense, each component of the input is convolved with the Fourier transform of the sampling frequency, fc, to give a sin x/x amplitude response modifier at the output. This, of course, assumes an ideal output smoothing filter. The first "zero" of the sin x/x amplitude modifier occurs at the clock frequency. Thus, at the proposed maximum useful input frequency of fc/2, the output amplitude would be down to .637, or a 4 dB loss. Any realistic viewpoint should also consider the less than ideal rolloff characteristics of output filters, and the possibility of charge dispersion inside the delay line itself.

In a bucket brigade device, each shift of the charge packets leaves behind residual charges, picks up charges from switching signals induced into the audio path, and (at higher frequencies) can radiate energy from the delay line path. All these problems cause inefficiencies which are accumulated over the length of the delay. These inefficiencies account for most of the "Noise" or distortion typically associated with analog delay lines. However, the Reticon 8AB-1024's utilization of N-channel technology provides better noise and dynamic range specs than their P-channel counterparts. The typical 70 dB dynamic and noise ratio of the SAD-1024 is perfectly adequate for most experimental applications, and noise gates or companding noise reduction is easily implemented with the delay lines in finished versions of circuits requiring higher specifications.

ABOUT THE EK-5



The small amount of circuitry involved in the EK-5 is the minimal configuration required to get the chip into operation. Naturally, more complicated or refined applications will require additional circuitry. Positive power is applied to pins 7 and 9 through the decoupling network consisting of R3 and Ø2. This helps stabilize the supply and keep noise from getting in or out. Trimmer R1 and current limiter R2 are used to apply bias at the input, pins 2 and 15. The voltage at the input pins must be set to 40% of the supply voltage in order for the IC to pass a signal. An input signal of up to 500 mV peak-to-peak can be applied to the input pin via coupling capacitor C1. Note that the polarity of this capacitor assumes a ground referenced input signal. If you are using circuitry which places the audio signal on a DC level higher than the 8AD-1024 bias voltage, you will need to reverse the polarity of C1. The primary output, providing 512 clock half cycles of delay, and the secondary output, providing an extra half period of delay, are selected from pins 5 and 3 (12 and 14) respectively. R4 provides capabilities for varying the gain of each output in an inverse ratio. This allows matching the two output stages so the DC levels of each output are the same. In this way, the clock signal on which the audio signal rides is minimized due to cancellation in the mixing process. R5 serves as the delay line load on which the summed signal is dropped. C3 is a crude passive filter to help further eliminate some of the clocking glitches and noise above 15 kHz. or so. Despite the inclusion of this filter, additional output filtering with a sharper cutoff should also be used to reduce clock noise modulation of the audio signal. C4 serves as the output capacitor which has a polarity to drive an assumed ground referenced load. As with the input capacitor, if you will be driving a load with a DC component higher than the DC component of the signal on R5, you will need to reverse the polarity of C4.

To drive the bi-phase clock inputs of the SAD-1024, one half of a 4013 flip-flop is used. The Q output is tied back to the Data input to generate a divide-by-two circuit. The clocking input to the divider is fed from transistor driver Q1. This way, you need not feed the EK-5 clock input from a full logic level equal to the supply voltage of EK-5. External clocks can be as simple as a low level (down to about 1 volt peak) differentiated spike from a simple UJT oscillator, or a full logic level clock generated by optional on-board components. The rest of the circuitry on the EK-5 board is an exact duplicate of the first half, except using the other halves of the ICs. Also provided in the EK-5 layout are two sets of uncommitted component mounting holes, each of which can accommodate a 16 pin IC, or smaller 14 pin IC, or even two 8 pin ICs plus locations for required resistors and capacitors.

The edge of the EK-5 board is configured to fit into a 22-point edge connector with .156 inch spacing between connections. This style connector is readily available as a 44-point double-sided edge connector from your local Radio Shack stores or many mail order parts houses. Alternatively, you can use the copper fingers as solder points for hardwired applications. Four corner holes allow mounting the circuit board with #4 size hardware.

APPLICATIONS



There are several ways that the two independent delay sections can be used in conjunction with each other. The normal single section configuration involves using only half of the SAD-1024 as shown in figure 5. This is the basic set-up used in EK-5 and described previously. The serial configuration doubles the permissible delay time for any given sample rate. To accomplish this, the output from A is slightly attenuated to restore the original input level (see figure 6). This initially delayed signal is then applied to section B. Note that both Ø1 clock lines are tied together, as well as the Ø2 lines being driven from a common source. Output A' need not be used in this configuration, as the input to section B is disabled during the same time period in which output A' is inactive. For both these configurations, note that there is only one sample per clock cycle, but two clock "glitches" in the output.

Figure 5


Figure 6


For more critical applications, there are two methods which provide slightly better signal reproduction, at the cost of less delay (you always have to pay a price!). Parallel-Multiplex configurations (see figure 7) supply two analog delay line sections with identical signals, however the clock lines to the two sections are reversed. That is, the clock line used for Ø1 in the A delay line is used for Ø2 in the B delay line, and so on. In this way, samples are alternately taken by the two delay line sections thus providing twice as many samples for a given clock frequency. This circuit uses one output from each delay line to be summed as usual for reconstruction of the input signal and nulling of the clock glitches. This circuit configuration was used in the PAIA Phlanger. Note that in any of these configurations where one or more of the output pins are not used, the unused pins should be tied to the positive supply to disable the internal source follower FETs.

Figure 7


In the Differential configuration, it is easier to obtain cancellation of clocking glitches and even-harmonic distortion. As shown in figure 8, each half of a differential signal is applied to each half of a delay line. At the outputs, the normal (A and B) outputs are summed with the extended (A' and B') outputs as usual. This delayed differential signal is then applied to a differential amp where the "common" clock glitches are cancelled.

Figure 8


Any of the above methods can be combined for multiple chip operation. For example, you may wish to use the differential mode for low clock noise feedthrough, plus the techniques of serial configuration for longer time delay. Possibilities are numerous, and each has benefits for particular applications.

With all the above information out of the way, you should have a fairly good idea how the SAD-1024 works, and how to use it in its own audio delay subcircuitry. Now you are ready to fit the EK-5 delay circuitry into whatever application you have in mind. Some effects are obvious. For example, an echo unit would be configured by using a chain of delay lines (to get a long enough delay to be able to actually hear the "echoed" signal) and a mixing amp to provide an output signal containing the original input and the delayed signal. For fancier versions, you could provide front panel control of the clock speed to vary the time of delay. And, how about a control to tap off part of the output of the delay line and feed it back to the input for repeating echos. All these features would be desirable in an echo unit. All are straightforward and easily implemented, so we won't go into any detail here. A few more advanced applications, and guidelines for their implementation, are presented below.

Reverberation, although very similar and often times confused with echo, is a complicated and delicate effect to synthesize. Multiple delay paths, each with different delay times, provides the basis for reverb, as it simulates sound waves bouncing off various walls and structures in an enclosed area. To provide the effect of multiple reflections and persistence of the reflected sound, a feedback path should be provided to send the various delayed signals through additional (different) time delay paths. Figure 9 shows a block diagram for such a system. A minimum of four independent delay paths is recommended to provide the randomness required for reverb. Of course, additional paths help the system do an even better simulation.

Figure 9


Vibrato can be obtained by slightly modulating the high frequency clocking signal for the delay line. The resulting pitch shift is the derivative of the waveform being used to modulate the clock. Thus, a sine wave used to modulate the clock will provide a cosine variation of pitch, or the most common smooth vibrato effect. Using specialty waveforms can produce special effects. Modulating the clock with a triangle wave can produce a square wave vibrato. Using a ramp will provide a constant shift of the pitch — shifting up if the ramp has a positive slope, down if it has a negative slope. Unfortunately, the solid pitch shift is marred by the flyback period of the modulating ramp wave. Additional circuitry can solve this pitch "glitch", but the configuration is far from simple. Here's how the vibrato works (basically). When the signal has been passed through the delay line, it is clocked out of the delay line at a slightly higher clock speed than when it went into the line, the pitch of the signal will be raised slightly. If it is clocked out slower than normal, the pitch will be lowered. The continuous cyclic variations in the clock speed then translates to the variations in pitch of the signal — vibrato.

Chorusing is very similar to vibrato in that you wish to make small variations in the pitch of the signal. However, to best simulate the effect of two or more independent signal sources, a random fluctuation of clock speed more closely approximates the random technique differences between human-type musicians. Summing the original with one delayed signal can give the effect of two musicians playing in unison. Adding either another delay path with its own independent random clock signal, or using another delay stage to double the first doubler output (as shown in figure 10a) should be sufficient to confuse the ear into thinking it is hearing not three or four instruments, but a rather large group playing in unison. Initial delay times as short as 1 millisecond can be used for the chorusing stages as shown in figure 10a. However, the effect seems to be more pronounced and realistic with initial delays in the neighborhood of 10 to 20 milliseconds.

Figure 10


Figure 11


Figure 12 (a)


Flanging is probably the most popular effect of the seventies. Without analog delay lines, this effect would not be a commercial reality. For flanging, a delayed signal is mixed with the original while the clock signal for the delay line is slowly varied across a wide range. Delay time span for a typical flanger is from about .5 millisecond to about 10 milliseconds. Figure 10b shows a block representation of such a system. Also, see the flanging article in the April/May issue of POLYPHONY. To easily accomplish flanging (or vibrato or chorusing) you will probably want to use a voltage controlled clock rather than varying clock speeds manually. A typical manually controlled, low-cost clock could be generated as shown in figure 11. Alternatively, extra money could be invested in using a 566 type VCO which is a much more versatile clock. It is also much smaller than a "gatetype" clock, so TWO of these 566s could be put on the EK-5 board where you could fit ONE of the 4001 or 4011 types. The basic connections to the 566 are shown in figure 12a. NOTE that a bipolar supply is required, but the square wave clock output switches between +V and ground which is perfect for driving our 4013 clock shaper. For using the 566 as a high frequency clock, the timing capacitor (at pin 7) should be small. The values between 15 pf and 100 pf generally work well, depending on application you are using the delay line in. Pin 5 is a frequency modulation input, but only operates over a narrow voltage range and only delivers a frequency deviation (predictably) of 2:1, or up and down one octave. For a wide range clock sweep it is best to tie pin 5 to a fixed reference and play with the timing resistor input at pin 6. A fixed resistor or pot can be used as shown in figure 12b and c. Best yet, a voltage controlled current source similar to figure 12c can provide clock sweeps over several decades for flangers and wide range echo systems. For additional information on using the 566 as a voltage controlled oscillator, see Lab Notes in the November, 1977 issue of POLYPHONY.

Figure 12 (b)


Figure 12 (c)


Figure 12 (d)


As mentioned earlier, don't forget to use output filters to roll off the response of the delay line at a point at least 1/2 or 1/3 of the clocking frequency. This is important for minimizing clock frequency feedthrough and intermodulation of clock frequencies with audio signals. A typical output stage utilizing a two-pole active filter with a cutoff frequency of 20 kHz. is shown in figure 13. Your filter need not be this complex for initial experimentation, but don't discount its importance if you experience noisy output.

Figure 13
(Click image for higher resolution version)


I wish to thank the people at RETICON for allowing us to use many of the drawings and ideas from the manuals and data sheets they have published. Their well-planned publications have been instrumental in letting many a designer get down to the business of applications rather than first spending a lot of time just learning how the chip works.

Hopefully, this will get you interested in playing with one of the neatest ICs to come around for some while. The EK-5 experimenter's kit is available from PAIA Electronics, (Contact Details) for $24.95 postpaid.


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Publisher: Polyphony - Polyphony Publishing Company

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Polyphony - Jul/Aug 1978

Donated & scanned by: Vesa Lahteenmaki

Feature by Marvin Jones

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