The Spectrum Synthesiser (Part 2)
Part 2 of this constructional series describes the keyboard controller
Figure 2 shows the circuit diagram of the keyboard controller. Connections 1 and 2 are the bottom and top respectively of the keyboard divider chain. This is arranged in the feedback loop of IC3a, which drives a current of about 1.8mA through the divider chain. This generates 8.3V across each divider chain resistor, corresponding to a semitone, and 1V across each group of twelve, corresponding to an octave. R58 and R59 drop 1.7V so the range of key voltage is 1.7 (top C) to 5.7V (bottom C). R57 and RV3 determine the current, RV3 allowing it to be trimmed for exactly 1V/octave.
IC3b generates a signal that is used, after processing, to gate the envelope generators and key voltage sample-and-hold. With no keys depressed, the non-inverting input is held low by R60 and since the inverting input is at +0.83V (determined by R58 and R60) IC3b's output is at its negative extreme, almost -15V. When a key is depressed, the voltage at the inverting input rises to between 1.7 and 5.7V since the gate bus-bar is connected to the divider chain by the contact of the depressed key, and the output of IC3b goes high.
TR3 is an FET which acts as a voltage controlled switch in the sample-and-hold circuit around C11. It is normally held off by the negative output voltage of IC3b, via R62 and D14, but upon this going positive it is turned on and C11 charges to the voltage on the S/H bus-bar (connection point 3). Since the contact spring makes with this before the gate bus-bar, the new key voltage is always ready for sampling by the time the FET is turned on. IC5a is an FET input op-amp with a very low input bias current. This ensures that when the key is released and TR3 turns off the charge on C11 is retained with the minimum of droop. With the 50pA worst case input bias current of the buffer amplifier, it takes about 13 minutes for the pitch of the oscillators controlled by the keyboard to drop one semitone.
With the output of IC3b low, C10 is kept charged by D11, but when a key is depressed it is allowed to discharge through R65 and R56. It takes approximately 2mS for the voltage to reach the threshold of the schmitt NAND-gate IC6a, the output of which then goes low. Since D11 charges C10 very fast upon the comparator output going low, it must remain high for at least 2mS for the gate signal to be passed on to IC6b. This ensures that the effect of contact bounce upon key depression or release is eliminated and cannot cause false triggering of the envelope generators.
The external gate signal is inverted by TR4 and NAND-ed with the output of IC6a to give the key gate signal which is sent to the EG's.
If a new note is played on the keyboard before the previous one is released, a new CV is generated, but since the key gate signal remains high, the EG's will not restart their envelopes. This can be a problem when percussive envelopes are used, fast keyboard runs giving missed notes. The problem is eliminated by detecting a change in CV at the sample and hold output, and generating a key retrigger signal for the EG's. IC4a is a high-gain differentiator that produces a pulse for each change in the value of the CV. These pulses are rectified and squared up by the comparator IC4b, and lengthened by D16, R75, and C12 to a minimum of 5mS.
Contact bounce produces a very ragged CV change when a note is depressed while one is already down, and this in turn produces a multiple pulse at the output of IC4b. The circuit around IC6c generates a clean 500uS pulse from this signal — most important for external devices such as sequencers which count in response to triggers from the keyboard. When the charge on C12 reaches the threshold of IC6c, the output goes high and C14 charges via D18 and R85. After 500uS, C14 also reaches the required level, the output is forced low, and C14 begins to discharge slowly through R81. For 30mS after each pulse C14 inhibits IC6c so that no more pulses can occur at the output during this period.
Since the sample-and-hold voltage is updated before the key gate starts, a first key depression would cause an unwanted pulse on the key retrigger line. This is eliminated by D17, which holds the input of IC6d high until the gate is received.
The de-bounced gate signal from IC6a is inverted by TR5, which drives the 'key gate out' interface jack. D19 causes the gate out signal to go low in response to the key retrigger signal. TR5 is arranged to pull the output to +15V to generate the gate signal — this system allows gates from different sources to be connected together, providing an OR-function that gates the controlled device if any source signal is high.
The output of the sample-and-hold circuit (TR3, C11, IC5a) is passed to the glide circuit (R74, RV4, C13, IC5b) which produces sweeps between successive notes. The time taken for a new note voltage to be reached is controllable from almost instantaneous to five seconds for one octave by RV4. IC5b is a low input bias current op-amp, avoiding any voltage drop across RV4 that would cause a perceptable pitch error with maximum glide.
IC7a inverts the output of the glide circuit, and applies an offset so that the middle 'C' of the keyboard generates a key CV of 0V. This simplifies interfacing with additional equipment. The 'Tune' pot. (RV5) shifts the pitch up to + 2 semitones. R90 limits the current supplied by IC7a but does not affect the voltage under normal conditions. This is required since the CV is momentarily shorted to earth when the other end of the patch lead from JK2, the 'key CV out' interface jack, is plugged into another piece of equipment.
Feature by Chris Jordan
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