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Technically Speaking (Part 1)

Article from Making Music, April 1986

Getting started on a project to build a MIDI interface for a BBC micro and a DX21 synth

Techno-philes, start here. Andy Honeybone, computer expert and keyboard thrasher of some note, dives deep into the world of chip-music. We begin with a project to build a MIDI link running Yamaha's DX21 FM synth from a BBC micro. And how. Part two next month.

Stuck, as ever for an opening paragraph, I turn to my miniscule French dictionary to dredge up some dire pun about MIDI meaning mid-day. But under the dictionary entry there is more - a colloquialism, "chercher midi a quatorze heures" - to see difficulties where there are none. Tenuous but true, a real windfall for a hack poised to begin a new series exploring MIDI and hi-tech.

The first project is the design of a MIDI interface for a BBC microcomputer. Although the BBC is rather old hat, its entrails are well documented and I've got one (a BBC, not an old hat).

The story begins in my local branch of Tandy where I spot a likely piece of IC-LSI Perfboard (cat. No. 276-162) which looks just right for a MIDI interface. The Perfboard is then matured for six months on various shelves at my abode and narrowly avoids being lost down the back of the sofa.

Then the DX-21 arrives. Suitably motivated, the design and construction is begun.

MIDI, as we know, is a 5mA current-loop optically-isolated serial interface operating at 31.25 kbaud. This will not be the column where bytes are explained every month. Such explanations, within the topic of microprocessor interfacing, would be like describing cash to a man who's just walked into a casino. These utterings are intended to advance and direct those who already know which way is up.

The hardware of the interface divides neatly into four blocks: the address decoder, the clock, the serial/parallel converter, and the TTL level to current loop circuitry. Let's deal with the first, first.

The asynchronous communications interface adaptor (ACIA) chip which is at the heart of the interface requires two unique addresses in the memory map of the Beeb. One will be the address of the data register and the other, the control register. The actual addresses available for our use are subject to considerable constraint through prior claim by internal workings and external add-ons. The One Megahertz bus allows the connection of 255 memory mapped devices of which only those addresses between &FCCO and &FCFE are unreserved. Within this space addresses &FCFC and &FCFD have emerged as favourites for a MIDI interface and it would be pointless to choose differently simply on the grounds of wanting to appear original.

The BBC gives an output for addresses &FCxx called NPGFC (Not Page &FC) but, alas, this suffers from glitches resulting from the 2MHz system clock being stretched to cope with slow I/O devices. Acorn suggest a clean-up circuit using NOR gates and not being one to enjoy re-inventing the wheel, I have incorporated their design. Additional circuitry is required to decode the lower seven bits of the address bus to give an enable signal, valid for both &FCFC and &FCFD. Final selection is performed on the ACIA chip to which address line zero is connected directly. The 74LS30 eight-input NAND gate gives a low output when all its inputs are high. Inversion of address line A1 gives this condition for our required range. The low order address selector signal is combined with the cleaned NPGFC line in a flourish of negative logic by the spare 74LS02 NOR gate.

Fortunately, a clock signal is available on the 1MHz bus. A clock of 31.25kHz is required but the BBC gives, not surprisingly, 1MHz. The ACIA chip has the ability to divide the incoming clock by one, 16, or 64 times. The MIDI clock rate was defined as the seemingly illogical above quoted value as it was easily obtainable by division of a 2MHz system clock by 64. As we have access to a clock rate of half that, our divisor has to be 32. The chip does not give us this option and so we must call in some extra hardware in the shape of a binary divider to pre-scale the clock by two. Using the divide-by-16 option on the ACIA chip we end up with the required clock. Connecting the not Q output of a D-type flip-flop (74LS74) to the data input gives a binary divider.

This gust of technical description should give you enough to chew on for a month. In the next issue of Making Music, I'll continue the hardware description and present brief programs for testing.

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Series - "Build a MIDI Interface"

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Part 1 (Viewing) | Part 2 | Part 3

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Song for the Sideman

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Synth Sense

Publisher: Making Music - Track Record Publishing Ltd, Nexus Media Ltd.

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Making Music - Apr 1986



Electronics / Build



Build a MIDI Interface

Part 1 (Viewing) | Part 2 | Part 3

Feature by Andy Honeybone

Previous article in this issue:

> Song for the Sideman

Next article in this issue:

> Synth Sense

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