Why isn't everybody happy with 16-bit sampling? Why are 20 bits better than 16? Kendall Wrightson looks at the technology in the latest generation of analogue-to-digital convertors.
Leaf through a typical hi-fi magazine and you're bound to find at least one reference to the 'harsh', 'cold' or 'metallic' sound of digital audio. Although these criticisms are extremely subjective, most engineers would agree that audio loses something in the process of being translated into the digital domain. The electronic component responsible for this translation is the analogue-to-digital convertor (ADC), and over the past two years, ADC designers have developed new techniques in an attempt to overcome the critics' objections to digital sound.
Two main factors determine an ADC's performance — sample rate (the number of times per second at which an audio signal is sampled) and resolution (the number of levels used to describe its amplitude).
The sample rate determines the range of frequencies an ADC can adequately handle, and it is expressed in samples per second, or kHz — '44.1 kHz' means 44,100 samples per second. An ADC's sample rate should be at least double the highest frequency it is required to convert, otherwise it will 'alias' — ie. produce whistling tones that are harmonically related to the sample frequency. (The man who made this discovery was called Nyquist, and the upper limit of frequencies that can be properly recorded — around 20kHz in the case of CD standard digital audio — is therefore referred to as the Nyquist frequency.)
Quantisation resolution can be expressed either in bits, or as a number of discrete levels. As a bit can only have two values (0 or 1), an 8-bit ADC can describe 2 to the power of 8 (= 256) levels. A 16-bit system would yield 65,536 levels (2 to the power of 16). The greater the resolution of a convertor, the more accurate will be its representation of a sound.
The example in Figure 1 shows a sine wave being sampled with a resolution of 16 levels — a 4-bit convertor. The input sine wave has a frequency of 1 kHz, therefore its period (1/1 kHz) is 1ms. During one period, 20 values are sampled, and the sample rate is therefore 20kHz (one sample is taken every 50 microseconds.)
The number of bits an ADC uses to quantify the amplitude of an audio signal determines its maximum signal to quantisation noise ratio. Quantisation noise is effectively the difference signal between the analogue input and the ADC's digital representation as illustrated in Figure 2.
The signal to quantisation noise ratio can be calculated by multiplying the number of bits by 6dB. Thus a 16-bit ADC is theoretically capable of (6dB x 16 bits =) 96dB. (This compares with a mere 55dB S/N for an analogue cassette recorder without noise reduction).
The major standard for digital audio is 16-bit quantisation at 44.1 kHz or 48kHz, which allows recording of the full range of frequencies that the average human ear can detect, and offers a maximum 96dB signal to quantisation noise ratio. While there have been few complaints regarding sampling rates, recording engineers have been demanding an increase from 16 to 18 and 20-bit quantisation. But why aren't 16 bits enough?
With either analogue or digital recording, achieving the optimum recording level is critical since under-recording produces noisy results while over-recording leads to audible distortion. Thanks to the effects of tape saturation, transient peaks may well illuminate an analogue recorder's overload indicators, without necessarily producing any audible distortion. Some say this saturation is the key to analogue's warm sound.
A digital recorder is not so forgiving, and even the swiftest of transients will produce distortion which is very audible indeed, and not at all warm. This is because an ADC has no saturation effect — once all 16 bits are set, that's it.
For this reason, digital recording levels are generally set slightly lower than on an equivalent analogue recorder. This reduces the overall signal to noise ratio since the loudest signal may set only 14 bits (giving 84dB S/N), while the quietest may be as low as four bits (24dB S/N).
In addressing themselves to this problem, the chip manufacturers' initial response was to modify their original ADC architecture to incorporate a technique called 'successive approximation' (SA). However, this approach proved futile due to speed limitations inherent in the SA design.
Designers then turned their attention to the oversampling techniques which had been developed to improve the performance of digital to analogue convertors (DACs), and in applying these to ADCs, a solution was found.
When you think about it, an ADC sampling at a higher rate than the standard 44.1kHz or 48kHz must reveal more information about the analogue input signal. ADC designers realised that there might be a way of transferring the additional information from the time domain into the amplitude domain — ie. use a higher sample rate to increase the effective quantisation level. Through the process of oversampling and decimation, this digital juggling trick can be accomplished.
Figure 3 shows a block diagram of an ADC which performs 64 times oversampling. It incorporates a 4-bit flash convertor (a fast, highly accurate ADC which does not use the SA technique), and its sample rate is 3.072MHz (64 x 48kHz). The 4-bit output passes into the noise shaping circuitry which transfers ADC quantisation noise outside the audible 20Hz to 20kHz range. How this is achieved is a major article itself, and need not concern us here.
The third stage in the conversion process involves a digital decimating filter, clocked at 48kHz, which produces one 10-bit sample for every 64 input samples. It does this by making fast calculations in real time from coefficients stored within its on-chip ROM (Read Only Memory).
Thus, the time-to-amplitude transfer has been achieved, and the 10-bit resolution of the whole process has been obtained with a 4-bit convertor. With a sufficiently high sample rate there's no reason why an oversampling convertor could not provide 18 or 20-bit quantisation. In fact, American chip manufacturer UltraAnalog already produce an oversampling ADC capable of 20-bit stereo conversion, which Data Conversion Systems have built into their 1U DCS 900 stand-alone convertor unit.
The latest technique in analogue to digital conversion is Delta-Sigma modulation, a 1-bit process originally devised 30 years ago for low bandwidth telephone signals. However, as Figure 5 shows, Delta-Sigma modulation is quite unlike the standard 'quantifying' ADC process illustrated in Figure 1, where more bits mean better performance. In fact, the Delta-Sigma ADC makes no attempt to measure or quantify the analogue signal at all.
The Delta-Sigma technique is based on the same principle as a servo device — error correction. Any servo system works by comparing its input with its output at regular intervals. A simplified block diagram of a Delta-Sigma ADC is shown in Figure 4. The integral comparator compares its own digital output (converted into analogue form by the single-bit DAC) with the analogue input once every clock pulse. Referring to Figure 5 again, during clock pulses 0 to 2, the comparator output (signal B) remains at zero, which when converted by the 1-bit DAC produces the steadily increasing signal A.
By the leading edge of clock pulse 3, the input signal is higher than the comparator's converted output, so the comparator output changes to a ' 1', which is then converted to a steadily decreasing signal... and so on.
In effect, the comparator is 'tracking' the analogue input. The more frequently it compares its output against the analogue input — ie. the higher the sample rate — the more accurate the tracking. The final stage of the Delta-Sigma convertor is the decimating filter, which converts the single-bit comparator signal into a 16-bit output.
It is generally accepted that Delta-Sigma ADCs (and DACs) produce a less harsh, more natural sound than any other conversion method. This is because the possibility of gross errors is eliminated since the input is tracked rather than measured.
Stereo Delta-Sigma ADCs are already used in domestic DAT machines such as Aiwa's portable FHDS1 DAT. In the professional area, the only units that have so far adopted the technique are Digidesign's Pro I/O (a combined stereo ADC/DAC which forms part of the Sound Tools tapeless recording system), and the Aiwa/HHB Pro 1, a pro version of the HDS1.
When the Audio Engineering Society and the European Broadcasting Union put a specification together for a serial digital audio interface, they very astutely decided to allow for the possibility of up to 24-bit samples. With rumours from Japan that a 20-bit domestic compact disc system is under development, many pro audio manufactures are known to be designing 20-bit ready systems.
Several manufacturers already offer devices with greater than 16-bit recording ability. Mitsubishi's X86C master recorder offers a 20-bit record mode, and the new Yamaha DMR8 cassette based multitrack utilises a 19-bit format. Waveframe's AudioFrame and the Symetrix DPR44 tapeless recorders both boast 24-bit capability.
Meanwhile, the ADCs found in some digital multitrack machines and tapeless recorders are now looking and sounding well out of date. Studios are therefore beginning to invest in the latest dedicated ADCs.
The current crop of 18, 19 and 20-bit ADCs employ the 4-bit oversampling technique described earlier, however several heavyweight chip manufacturers are now producing 20-bit Delta-Sigma convertor chips, so we can expect to see them in pro audio products very soon.
And what of analogue warmth? Well, maybe we just have a choice between simulating it digitally, or getting used to the natural sound of Delta-Sigma conversion.
Thanks to Tim Orr and Carl Schofield for their technical assistance in compiling this article.
Feature by Kendall Wrightson
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