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Powertran MCS1 (Part 3)

How it Works

Part three, and a look at the design thinking behind this astonishing MIDI-controlled sampling unit.

Last month saw the MIDI Controlled Sampler's circuit diagrams reproduced in full. Now we take a look at what those circuits add up to in real life.

To re-cap for those who might have missed the first two parts of this series, the Powertran MCS1 is a digital delay unit that can also act as a sound-sampling device. This means that in addition to providing all the commonly used time delay effects such as chorus, echo, flanging and so on, the MCS is also able to sample externally-generated sounds digitally and store them in memory. The pitch of the stored sound can then be altered via either a MIDI keyboard or a one-volt-per-octave one.

The description that follows refers to the four circuit diagrams we published in E&MM November, so it's important you have that issue in front of you, otherwise you won't understand a word of it (some of you probably won't understand a word of it anyway, but...). Although the reproduction of some parts of the circuit wasn't quite as good as we would have liked, you shouldn't experience too many problems in identifying which bit goes where.

With luck, this description should assist newcomers to the world of electronics design in getting acquainted with some of the principles behind the MCS1, as well as giving experienced readers a detailed insight into how well-tried design conventions have been applied carefully to make the Powertran unit a high-performance machine whose cost-effectiveness is second to none.

Diagram 4

I know it sounds strange, but let's kick things off with a look at the last of the four drawings published in November.

IC 400 is a variable-gain preamplifier whose input sensitivity can be selected for high-level or low-level operation from a low-impedance microphone. The RC4558 is a low-noise op-amp that's used at various points throughout the MCS1's design.

Figure 1. Anti-aliasing filter comprising IC401, 402.

IC401 forms a four-pole low-pass filter followed by IC402, which forms a notch. The combination of these two creates an elliptic filter (Figure 1) with a 12kHz low-pass response and a notch at 24kHz: this filter stage precedes the mobile tracking filter, IC403. This is a switched-capacitor four-pole low-pass filter presented in an eight-pin package and manufactured by National Semiconductor. The break frequency is determined by dividing the input clock frequency by 50 (ie. MFCK/50). The package is used in this circuit as an antialiasing filter (see Part 1, E&MM October, for an explanation of aliasing and what can be done to eliminate it), but seeing as it is itself a sampled-data device, it needs an anti-aliasing filter of its own, albeit at a frequency 50 times higher. This explains why the fixed active filter precedes the mobile one.

A further low-pass filter, IC404, is used to provide further filtering and to remove any high-frequency clock breakthrough from the mobile filter. The MF4-50 (IC403) is claimed to have a dynamic range of 80dB. In other words, it can pass a peak signal of 2.8V rms and the residual noise, band-limited to 20kHz, will be 0.282mV rms. I measured it and made it 79dB, which for a noise measurement is very close. Anyway, the second half of IC404 is the pre-emphasis circuit, and this can be switched on to give treble lift, thereby masking quantisation noise (again, see Part 1 for details) at the deemphasis stage. The complete anti-aliasing filter stage is shown in Figure 2.

Figure 2. Complete anti-aliasing filter.

The signal is now ready to be converted into digital data by the analogue-to-digital converter.

IC405 is a sample-and-hold device, and this freezes the analogue signal long enough for a conversion to be performed. The ADC itself comprises IC406 (a fast voltage comparator), IC408 (a successive approximation register, or SAR for short), IC409 (a companding DAC set in encode mode) and IC407 and 410, steering logic.

How does the converter operate? Well, the SAR is given a command called SC (for Start Conversion) and a clock signal, ADCK. The SAR then performs a series of tests on the frozen analogue input, and these are as follows.

First, it tests the MSB (Most Significant Bit) of the code to a 1 and all the others to zero: the DAC output can then be compared to see if it's bigger or smaller than the analogue input. If the DAC output is smaller (ie. less positive) than the analogue input, the MSB is stored as a 1. The next bit of the code can then be tested by setting it to a 1, and the whole process is repeated. In fact, all the bits are tested in this way, the results being stored by the SAR.

As this process continues, so the DAC output successively approximates towards the magnitude of the analogue input. After eight tests, the conversion is complete, and the DAC output is then equal to the analogue input, ± ½ LSB. As far as time is concerned, the whole conversion process takes nine ADCK periods, and when it's completed, the output data becomes stable and can be written into the memory.

Data is read from the memory by latching it into IC412 and then feeding it into IC413, a companding DAC set into encode mode. The DAC output can be seen at the output of IC414.

IC415 forms a four-pole low-pass filter, used to recover the analogue signal from the 'crunchy' DAC output. The signal is then filtered by another mobile four-pole low-pass filter, IC421. Some replay rates are very slow (perhaps as low as 2kHz), so the mobile filter has to track at least an octave below this if the 2kHz sampling rate is not to be too noticeable. Again, the mobile filter is followed by a fixed low-pass one, IC422: the second part of this is used to provide the de-emphasis circuit.

T402, T403 and IC424 form a simple voltage-controlled attenuator used in the MCS1 as a mute circuit, the first-mentioned being a junction FET (field-effect transistor). When the voltage on the gate is about -3V, the FET is turned off, and the channel resistance is about 50Mohms, the attenuation through the circuit in this mode being about 90dB. By comparison, when the gate voltage is 0V, the FET is turned on and has a channel resistance of only 400ohms. This attenuates the analogue signal as seen at the positive end of C441 to about ±60mVp, and therefore allows distortion operation through the FET. See Figure 3. The last stage of IC424 is an output amplifier driven by the mix between direct and delayed signals.

Figure 3. Mute circuit operation.

The MFCK signal that drives the switched-capacitor filters is generated by IC416, 417, 418 and 410. This is a phase-locked loop (PLL) which multiplies the system conversion frequency (CK/N) by a number between 8 and 32 - this is the filter offset. The break frequency of the mobile filters is given by the equation:

Fb = (CK/N x Z Hz) / 50
where Fb is the break frequency and Z the filter offset.

Circuit operation is as follows. The CK/N pulse is fed into the phase comparator of the phase-locked loop, while the output of the PLL VCO is used to clock a down counter, IC417. This counter counts down to zero, whereupon the RC output causes it to load in a four-bit code. The counter is then loaded with this code and proceeds to count down to zero again: thus a programmed division is performed. The RC output is divided by 2 by IC410, which generates the square-wave output fed into the other half of the phase comparator. The feedback loop is now complete.

The PLL VCO will adjust itself to be equal to CK/N multiplied by the total loop division number, the latch IC416 being used to store this number. Occasionally, the PLL will be commanded to generate an output frequency in excess of 700kHz, but will not be able to do this simply because its own VCO cannot exceed this frequency. And seeing as the MF4 mobile filters have a clock frequency maximum of 1MHz, this enforced limitation is actually desirable.

Diagram 2

The MCS1 memory is 64Kbits long, and therefore requires a 16-bit address counter in the shape of IC207, 208, 210 and 211. These counters are used to count through memory locations for both Record and Play functions. They can be set to any 16-bit address simply by being loaded with the data stored in latches IC206 and 209. This data is H0000 for the Delay Line mode and front panel-selectable in Edit mode.

A 16-bit comparator (IC201, 203) compares the memory address with the data held in latches IC200 and 202, and when the memory address is greater than or equal to the address stored in the latches, it generates a load pulse for the memory address counters. IC200 and 202 hold the memory end address and IC 206 and 209 the memory return address. See Figure 4.

Figure 4. Looping.

The logic hardware performs all the looping functions, with the MCS1's microprocessor merely setting up the two 16-bit parameters. Note that the circuit allows these parameters to be any number between the start and finish of the memory - this makes both very short memory lengths and continuously variable loop lengths possible.

IC212 and 213 are used to multiplex the memory address into the MCS1's DRAMs. First, IC212 is enabled, and the bottom eight bits of the memory address are entered into the DRAMs as the ROW address. Next, IC213 is enabled and the top eight bits of the memory address are entered as the DRAM's COLUMN address (see Figure 5).

Figure 5. Memory address timing diagram.

The DRAMs are actually 64K dynamic devices and are refreshed by performing ROW reads. This is why the fastest moving part of the memory address (the LSB end) is used to select the ROWs. In fact, many of the refresh requirements are generated by the natural reading process. The refresh time as quoted by manufacturers is usually between 2 and 4 milliseconds: that is, the refresh electronics should perform a dummy read on each row every 2-4mS. If for some reason this doesn't happen, there's a possibility that the contents of the memory will be corrupted.

I've tested the MCS1 DRAMs myself and found they actually needed a refresh every 25 seconds, whereas the makers specify 4 milliseconds. They might from time to time get a duff memory cell that actually discharges itself in that time, but personally I have my doubts...

Anyway, to make absolutely certain that no refresh problems are encountered, a highspeed refresh counter (IC224) and buffer (IC223) are used to perform the dummy reads.

Data can be transferred from the DRAMs to the microprocessor data bus via two latches, IC222 and 225. These routes are used to transfer the memory data to and from the external floppy disk, and also to clean out the memory on powering-up the MCS1. Just to illustrate how important this function is, imagine getting 10 seconds of digital junk blasting out of the audio output every time you turn the MCS1 on.

Figure 6. Click-track signal.

Moving on, a click-track (IC227) uses the MSBs of the memory address counter to contrive a metronome beat, and a graphic illustration of this is shown in Figure 6.

Diagram 1

The whole delay line (but not the microprocessor) is driven from a master clock generator IC101, which runs at frequencies between 2.5MHz and 10MHz. The oscillator is voltage-controlled, and can therefore be controlled by a voltage from any conventional one-volt-per-octave music synthesiser. Obviously, this voltage has to be converted into an exponential signal by a simple log converter, and this is made up from IC121, T100 and T101.

As we mentioned in Part 1, a two-octave range can be obtained using the voltage control input, but the MCS1 can also add a large musical transposition to the output signal.

The voltage control is a Play mode function, and a two-way switch (IC107) selects either one-volt-per-octave or microprocessor control of the master clock generator. By using a latch (IC118), a DAC (IC119), and a low-pass filter (IC120), the microprocessor can generate sinusoidal sweep and pitch-bend control voltages.

The sinewaves are generated in software with a counter and lookup table. A number is generated by the sweep frequency controller (a panel function, this) which is added to the counter at regular intervals of time. The counter is used as a pointer to read the magnitude of the sinewave in the lookup table: as the pointer moves through the table, a sinewave is generated and turned into a voltage by the DAC. The number added to the counter determines the sinewave frequency - if the number is small, the pointer will take a long time to travel through the lookup table, and so on. The filter is used to smooth out the crunchy shape of the sinewave generated by the DAC, though it really isn't all that bad in the first place. If you want a visual representation of the software-generation of sinewaves, look no further than Figure 7. Incidentally, amplitude control of the sinewave is also performed in software, by a multiply routine.

Figure 7. Software-generated sinewaves using a counter-plus-lookup routine.

The control voltage electronics as a whole is actually rather difficult to align, while the master high-frequency oscillator contains a non-linearity which can cause detuning at low frequencies. The best musical results are obtained by optimising the log circuit for operation over the top octave range, because if you try to align it over the full keyboard range, tuning errors are simply inevitable. The MCS1's two-octave CV range is still useful for effects purposes, while CV devices can be used to drive the sampler over a six-octave range if you can get your hands on one of the analogue-to-MIDI converter units that are either available now or are soon to become so. You'll also need a MIDI keyboard, of course.

The master clock generator is fed into a divide-by-N down counter comprising IC102-104. The value of N is stored by latches IC105 and IC106. The counters count downwards to zero, and when they reach zero, an RC pulse is generated by IC104, and this loads the counters with the value of N. They then count down to zero again, so as you can see, they don't lead a particularly interesting existence.

The CK/N signal generated by this timing process is the sample rate of the system as a whole. Thus, by changing the value of N (N is a 12-bit word), the sample rate can be modified directly. In fact, this mechanism is used to vary the sample rate continuously via the control on the MCS1 front panel.

Additionally, and as a result of having a lookup table of values of N that result in a musical distribution of CK/N frequencies, it's possible for the microprocessor directly to control the pitch of the output signal in semitone steps. And yes, this control information can be obtained by decoding MIDI pitch data.

Now, while a source of MIDI codes can be used to generate the Play pitch for the MCS1, the method of dividing a master frequency by N to generate equally-tempered tuning is not without its problems. For one thing, N has to be an integer, and while this results in good pitch resolution for low notes, things aren't quite so consistent further up the scale. The overall resolution can be improved by increasing not only the size of N but also the frequency of the master oscillator: the MCS1 uses a maximum N value of 4096 and a maximum frequency of 10MHz.

On the basis of that 4096 figure, the first (lowest) octave has 2048 values of N at its disposal to define its 12 semitone frequencies, but the fifth (highest) octave has only 128. In other words, tuning resolution is still rather better at low frequencies than it is at high ones...

Moving still further ahead, ADC and read-write timing is generated by two counters (IC110,111) and a bipolar ROM, IC112 (again, see Figure 5). If the CK/N period is long, extra refresh counts are generated by the RAS and F!AE signals, ORed together by IC114.

Diagram 3

The microprocessor at the heart of the MCS1's design is a 6802, shown on the drawing as IC309. Strange though it may seem, this device generally has nothing much to do. It scans all the panel controls, loads up all the control latches and display registers, and then waits patiently for something to happen.

The reason for this inactivity? Simply that most of the MCS1's functions do not depend on the active intervention of the microprocessor for them to operate smoothly. The 6802's busy time is when it's generating a software sinewave or loading from or saving to floppy disk. A data bus buffer (IC321) has been used because the microprocessor would otherwise be unable to support loading on the data bus. The program is held in an EPROM, IC308.

A static RAM (IC307) is used as a scratch pad memory for items such as filter offsets and current values of N, while IC310-312 generate all the address decodes for the memory-mapped devices.

All the MCS1's front panel display details are handled by two chips, IC304 and 305. These are 34-bit long-shift registers with parallel outputs that can drive LED displays directly. Display data is entered serially as a 34-bit-long chunk, and the IC does the rest. No seven-segment decoding takes place inside the IC because the segments that have to be switched on are controlled directly by the input data stream. The four-digit display and the illuminated panel switches are driven by these ICs.

The pitch-controlling keyboard is scanned by IC315 and 316. The former pulls one row at a time low while the latter reads the keyboard in four-bit nibbles: any key depression is detected as a low voltage, and the six rows and read sequentially. IC316 also reads some of the other system signals.

IC328 is a control latch, the outputs of which are used to enable various functions. Serial data is handled by the ACIA (IC323), and transmission and reception between the ACIA, the BBC Micro (a future update), and MIDI is performed by enabling various tristate buffers (IC235, 326). The MIDI In signal is coupled to the MCS1 via an optoisolator IC327: this helps prevent the ground loops and other unwanted hiccups that so often occur while equipment is being interconnected.

The Gate, Audio and spin-wheel controller signals all generate a hardware interrupt (IC317, 318, 319, 320 and T300). When an external Gate signal occurs, it clocks flip-flop IC318, setting the Q output (pin 5) to a 1. This turns on T300, which in turn generates an interrupt. The microprocessor services this interrupt by reading the contents of bus buffer IC320. It discovers it was the Gate that caused the interrupt (the Gate signal is also available for reading at IC316), and takes appropriate action by generating a clear interrupt (CLINT) signal which sets the flip-flop back to a zero. The remaining two interrupts are similar.

The Audio signal is fed into a voltage comparator (IC317), and when the voltage at its input pins exceeds ±50mV, the interrupt is set: this circuit is used to trigger the start of a recording at the beginning of memory.

Figure 8. Spin-wheel controller.

The spin-wheel controller is an important part of the circuit because it is the manual interface between the user and the MCS1's internal control parameters. The controller (Figure 8) is a rotary switch with 50 positions per revolution: there are two switch contacts 90° out of phase with each other, and the rotation range is a full 360°.

Inside the MCS1, IC319 is used to detect the controller's rotation and the direction of that rotation. One switch output is used to clock a D-type flip-flop, the other provides the data input. If the rotation is clockwise, the Q output is set to a 1, and if it's anti-clockwise, a zero. The individual switch pulses generate an interrupt and need to be cleared if the next event is to be recognised.

The MCS1 software provides for three control sensitivities for the spin-wheel, these being Fine, Medium and Coarse. Just think, if you only got 50 'clicks' per revolution of the wheel in reality, it would take a grand total of 1310 turns of the controller to travel the full length of the MCS1's memory address.

The MCS1 retails at £499 plus VAT as a complete kit of parts, £699 plus VAT as a ready-built unit. Further information from Powertran Cybernetics, (Contact Details).

Series - "Powertran MCS1"

Read the next part in this series:

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Part 1 | Part 2 | Part 3 (Viewing) | Part 4 | Part 5

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Electronics & Music Maker - Copyright: Music Maker Publications (UK), Future Publishing.


Electronics & Music Maker - Dec 1984


Electronics / Build


Powertran MCS1

Part 1 | Part 2 | Part 3 (Viewing) | Part 4 | Part 5

Gear in this article:

Sampler > Powertran > MCS-1

Feature by Tim Orr

Previous article in this issue:

> Picture Music

Next article in this issue:

> Modular Synthesis

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