Chip Parade (Part 8)
The ubiquitous delay line
Robert Penfold takes a look at delay line chips for echo, reverb and flanging
Probably most readers will at some time or other have used a delay line, since these are used in a number of popular effects units, including flangers, phasers, solid-state echo and chorus units. Although there are several types of delay line, only two of these are in common use in musical applications. The most sophisticated type uses a digital technique which differs slightly from one system to another, but the basic idea is to digitise the input signal and then store it in RAM. After the required delay the RAM is read and the signal is converted back into analogue form. In practice the digitised samples are stored in successive RAM locations until the RAM is full, whereupon the system cycles back to the beginning and starts working through the RAM again. By continuously reading the RAM and appropriate number of locations behind the current storage point, any desired delay can be obtained. While this system can give excellent results in practice, even with very long delays, it is still rather expensive. Apart from the cost of two high quality converters (one A/D and one D/A), long delays require a large amount of RAM due to the high sampling rate that must be used (typically about 50kHz). Also, a 14 or 16 bit system is needed for optimum audio quality.
In due course the cost of digital delay lines will probably fall to the point where they can be used in low cost effects units and not just in the more sophisticated and expensive items of equipment. In the mean time analogue delay lines remain the only option for applications where a small, low cost delay line is required.
The analogue delay chips currently available all use the same technique, which is based on capacitors and electronic switches.
Looking at this system in a highly simplified way, it involves sampling the input signal with a capacitor, which is charged to the input voltage, and then passing on the charge from this capacitor to a second one. While the second capacitor passes on the charge to a third one, the input is again sampled by the first capacitor. Capacitor 1 then passes on its charge to capacitor 2, while capacitor 3 passes on its charge to a fourth capacitor. In a practical circuit there would be typically between about 200 and 3000 capacitors/switches, and the input samples are passed along all of these until they eventually reach the last one (and the output). This system of passing electrical charges along a series of capacitors is analogous to buckets of water being passed along a line of people, and it is from this that the term 'bucket brigade' delay lines is derived.
A clock oscillator is used to control the rate at which samples are taken and passed along the line, and the delay obtained depends on both the number of switch/capacitor stages, and the clock frequency. The delay is equal to the number of stages divided by double the clock frequency. The clock frequency must be at least twice the maximum input frequency, and should preferably be at least three times the maximum input frequency. This is the main limiting factor on performance, since it necessitates a clock frequency in the region of 50kHz in order to realise the full 20kHz audio bandwidth. With (say) a 1024 stage delay line this gives a delay of just over 100 milliseconds (1024/2 (2x50,000) = 0.01024 seconds, or 10.24 milliseconds). This is sufficient for some effects, but for those that require a fairly long delay, such as echo and reverberation, it is usually necessary to use a fairly long delay line together with a fairly low clock frequency. This gives an audio bandwidth that is often only about 4 or 5kHz, which can give quite good results, but is obviously less than ideal.
Delay lines, whether of the digital or analogue type, are usually preceded and followed by lowpass filters. The one at the input is used to prevent frequencies close to the clock frequency from entering the filter (which would give rise to an effect known as 'aliasing' distortion). The filter at the output is used to remove the clock signal which is effectively modulated onto the output signal. This occurs due to the sampling system which results in an output voltage that rises and falls in steps, but a high-slope output filter can eliminate the clock frequencies and give a proper audio output.
Another problem with analogue delay lines is that of a fairly high noise level when low clock frequencies are used. The fact that the audio bandwidth is rather limited helps to counteract this, but compander noise reduction systems are sometimes used with this type of delay line. Another point to bear in mind is that if the clock frequency is so low that it is within the audio band, a very high slope output filter will be needed to prevent audible breakthrough of the clock signal at the output.
If we now look at some practical bucket brigade delay line chips, the TCA350Z is about the cheapest and the shortest delay line available. It has just 183 stages, and is only really suitable for applications where a delay of a few milliseconds is required. The clock frequency should be in the range 10 to 500kHz, which corresponds to delays of between 9.15 milliseconds and 183 microseconds. Fig 1 shows the basic method of connection for this device.
It is very simple to use, with R1 to R3 providing a suitable bias voltage to the input of the device. In practice R2 is adjusted to optimise the large signal handling capability of the circuit. Inputs of up to about three volts peak to peak can be readily accommodated, and serious distortion only occurs with inputs of more than about six volts peak to peak. Provided the circuit is not overloaded the total harmonic distortion is typically only about 0.5% (3% maximum). Most delay lines provide a small amount of attenuation, and in the case of the TCA350Z the typical loss is only about 2.5dB.
There are two clock inputs to the device, and this is because a two-phase clock signal is needed. In other words, when one clock input is high, the other must be low, and it is just a matter of inverting a single phase clock signal to provide the second phase. This seems to be a characteristic of all the current delay line chips, and none of them seem to have a built-in inverter to provide the second clock signal. CMOS devices such as the 4047BE and 4046BE are ideal as the basis of a delay line clock oscillator. Fig 2 shows the circuit of a simple clock oscillator using the 4046BE. This has a control voltage input which enables the operating frequency to be modulated, and the delay time to be automatically varied (which is necessary for effects such as flanging and phasing). The specified values give a basic operating frequency of about 50kHz, but this can be altered by changing the value of C1. Changes in this value give an inversely proportional change in the output frequency.
For somewhat longer delays the TDA1022 is a popular choice. This is a 512 stage device and it will operate with a clock frequency of between five and 500kHz, which gives a delay range of 51.2 milliseconds to 512 microseconds. However, bear in mind that with a 5kHz clock frequency the audio bandwidth is at best only about 2kHz or so.
Figure 3 shows the circuit diagram of a basic TDA1022 delay line. This is similar to the one for the TCA350Z, but there are a couple of important differences. Firstly, the bias circuit (R1 to R4) includes an additional resistor. This is to give a small bias voltage to pin 13 of IC1. R2, as before, is adjusted to optimise the large signal handling performance of the circuit, and typically a signal level of 2.5 volts RMS gives only 1% total harmonic distortion. The second difference is the inclusion of R6 at the output, and this mixes the outputs from stages 512 and 513 of the device. Stage 513 does not provide any delay, but it is instead used to maintain the output of the unit when stage 512 is switched to receive the output from stage 511. It is not essential to do this, but by adjusting R6 correctly the output switching 'glitches' are reduced to a very low level, and this helps to give a good signal to noise ratio and low clock frequency breakthrough to the output. R6 can be adjusted for minimum output noise if an oscilloscope or AC millivoltmeter is available. Alternatively, the clock frequency can be reduced to an audio frequency, and then R6 can simply be adjusted to minimise the clock tone (which will be clearly audible on the output of the unit).
The attenuation through the TDA1022 is typically just 4dB. An excellent signal to noise ratio of 74dB can be achieved, but it is important to fully drive the circuit with a maximum signal level of around two volts RMS, and with long delays such a good noise level may be impossible to achieve.
Another 512 stage device is the SAD512D, but perhaps of more interest is the dual version, the SAD1024A. This has two 512 stage delay lines with separate inputs, outputs, and clock inputs for each section. It is therefore possible to use the two sections independently, but in most applications they are used in series to provide a 1024 stage delay line. Fig 4 shows the circuit diagram for the SAD1024A when it is used in this fashion.
As for the previous circuits, a bias network at the input is adjusted to optimise performance. Unfortunately, there is a DC shift through each delay line, and the first section cannot simply be direct coupled through to the input of the second stage. Instead a capacitive coupling must be used (C3), and a separate bias circuit is needed for the second section (R5 to R8). Like the TDA1022, a balance control is used to minimise switching 'glitches' at the output. It is not necessary to have a balance control at the output of the first section, and I have not found it necessary to use a load resistor here either.
The SAD1024 offers a creditable level of performance with a total harmonic distortion level of only about 0.5% with an input of one volt peak to peak, rising to 3% with an input of two volts peak to peak. The signal to noise ratio is better than 75dB. The clock frequency range is specified as 1.5kHz to 1.5MHz, which gives a delay range of 341 milliseconds to 341 microseconds. However, in order to give a reasonable audio bandwidth the clock frequency would need to be at least 10kHz, which gives a maximum delay of 51.2 milliseconds. This is sufficient to produce most of the delay line based effects.
For a few effects the maximum delay of the SAD1024 is inadequate. Also, solid state reverberation requires a delay line that has a number of tappings so that a range of delays can be obtained (the delayed signals simply being mixed together to give the reverberation effect). The MN3011 delay line chip has some 3328 stages, with tappings at stages 396, 662, 1194, 1726 and 2790. With a clock frequency of 10kHz this would give delays from 19.8 milliseconds at the first tapping to 166.4 milliseconds from the final stage.
Figure 5 gives pinout details of the MN3011. This device was used in the Chorus and Echo projects featured in previous issues of ES&CM, and those requiring circuit information on the MN3011 (and the matching MN3101 clock/bias chip) should consult these articles.
As mentioned earlier, high slope lowpass filtering is needed at the input and output of a delay line in order to prevent problems with aliasing distortion and clock signal breakthrough at the output. The filter requirements vary from one design to another, and in general, the lower the clock frequency the better the filtering must be. The circuit shown in Fig 6 is for an active lowpass filter having a cutoff frequency of 10kHz and an attenuation rate of 24dB per octave. This is suitable for use as an input or output filter, and if a higher attenuation rate is needed quite good results can be obtained using two filters in series. The operating frequency of the filter can be altered by changing the values of the filter capacitors (C2 to C5), and changes in value give an inversely proportional change in frequency (eg, doubling the capacitor values halves the cutoff frequency to 5kHz).
Feature by Robert Penfold
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