Digital Sampler/Delay (Part 2)
More from Paul Williams on this exciting new addition to the Tantek range.
Having generally described this exciting new module for the Modular Effects Rack, last month, Paul Williams now discloses more of the intricacies of the design, and takes a preliminary look at construction.
The audio signal presented to the unit remains in it's analogue form within the confines of the signal conditioning circuit shown in Figure 4. The incoming signal is buffered with variable gain by IC16a and presented to IC16b via the pre-emphasis network C12, R35 and R36. The signal then passes via IC17: a fourth order low pass switched capacitor filter which removes any ultrasonic component in the signal which might otherwise lead to aliasing with the VCO frequency. IC18a then mixes some treated (delayed) signal to the, as yet 'dry' signal under the control of VR10 (Regen). It's the output of this stage which is fed to the converter electronics for analogue-to-digital conversion. The output level of this stage is watched over by IC20a and IC19c and d forming a full wave rectifier. Any excessively high levels cause TR2 to conduct, pushing current into the control pin of IC19a, an Operational Transconductance Amplifier (OTA). The increased transconductance of this device then increases the negative feedback around IC16b, reducing its gain and thus bringing the output of IC18a down to an acceptable level. This limiting action is indicated by the LED D9, driven by TR1.
Treated signal from the DAC is received by IC21a, a sixth order low pass switched capacitor filter. Both the filters are under control of the VCO multiplier via the FCLK signal so that the maximum bandwidth possible is available for any given delay or sample time. The OTA IC19b, along with IC20b forms a Current Controlled Amplifier (CCA) with a deemphasis network C20, R59 and R60 to negate the effects of the pre-emphasis network, and at the same time reduce quantisation noise. The CCA is used to produce velocity sensitivity as we will see shortly. VR13 allows the mixture between the dry and treated signals to be varied, the composite signal being buffered by ICb with variable gain, and passed to the output.
The output of IC16a is precision rectified by IC21b, producing a DC voltage on C18 which is proportional to the input signal amplitude. When the signal ceases, the control voltage leaks away at a rate determined by the Decay control, VR12. This control voltage is only allowed to pass to the voltage-to-current converter, IC20c and d and TR3 when the unit is playing a sample, as dictated by the analogue switch, IC10c. IC10d otherwise forces the V-C converter to produce maximum current (ie. no attenuation). IC21c acts as a comparator to detect when the input signal level is above a preset triggering level, variable by means of the Threshold preset: VR11. A plug inserted into the gate socket overrides the precision rectifier, giving control of triggering over to the gate socket.
The operation of the module is timed and controlled by the logic shown in Figure 5 (next month). The Sample/Delay mode is set by the flip-flop IC24a, this being toggled by SW2 and indicated by the LED D15. This flip-flop controls the manner in which many sequences take place within the logic. The other flip-flops under manual control are IC25a for looping and IC23a for overdubbing, the latter can only be set when the sample mode is selected. Timing is predominantly controlled by the VCO, although the 6MHz clock and associated divider IC36 provide the other timings necessary for conversion and memory control. The address counters, IC37, 38 and 39 select the current memory address, this being updated at every VCO cycle. At each new address the VCO fires the monostables IC26a and b. Since the memory devices used are dynamic, they have to be refreshed every couple of milliseconds in order to keep the data intact. So that refreshing and read/write cycles do not clash, IC26b produces a BUSY signal a couple of microseconds before reading to indicate to the memory control when refreshing must be suspended. The process is similar when a write operation takes place at the end of a conversion, when the EOC signal fires the monostables IC27a and b.
When the preselected length of memory comes to an end, IC40 produces an END signal which sets the HOLD flip-flop IC24b. During the Hold period, conversions take place to digitise the Start and Length pots. The first conversion during Hold is for the Length pot, during which time the LNSG flip-flop IC28a is set. The digital word generated from the conversion is used to preset the down counter, IC40. The STAFF flip-flop IC28b then initialises the Start pot digitisation, the result of which presets the counters IC38 and 39. After this, the Hold mode is terminated, allowing address counting to continue from the start address loaded into IC38 and 39. Since IC40 counts down along with the address counters, it produces an END signal when the equivalent of the length pot digitisation has been counted through.
In the delay mode, no start conversion is produced since address counting always starts at zero. In the sample non-loop mode, the Hold state remains true until IC28a is triggered either by the TRIG signal becoming true with SAMOD true, or vice versa. The flip-flop IC25b causes sample playing to start at zero memory address when the unit is triggered and looping is selected. Subsequent loops start at the edited start point.
When the mode is toggled from Delay to Sample, the REC flip-flop, IC23b becomes set. Once IC28a becomes triggered, recording will start at the edited start point and continue for the selected length, when the END signal resets IC23b so that the recorded sample can be played. During recording, reading of the data already in memory is normally inhibited so that the setting of the Regen control does not effect the recording. Pressing SW4, the overdub switch sets IC23a along with IC23b for overdub recording. The only difference now is that the sample already in memory is played back simultaneously so that it may be mixed with the newly recorded sample using the Regen control.
Since the latest 256K DRAMs are used, the entire 64K byte of storage is contained within just two chips. The devices used, IC47 and 48, as shown in Figure 6 (to be published next month) have internal refresh address counters, so they simply have to be 'reminded' to refresh a new location at least every 16 microseconds. The RFRQ signal is raised by the control logic every ten microseconds or so, causing the memory strobing flip-flops IC44 and 45 to produce the appropriate refresh strobing sequence on each RFRQ pulse. The strobe pulses are timed using the master 6MHz clock.
Just before the memory is required to perform a read or write operation, the BUSY signal from the control logic prevents any new refreshes being initiated, whilst allowing time for any current refresh to be completed. To reduce the number of pins on the memory devices, the 16 address lines have to be multiplexed onto the eight address pins by means of IC42 & 43. The RWP signal causes a memory strobe sequence to be produced which strobes firstly the row address via IC42, then the column address via IC43 into the memory. The memory will then either read data onto, or write data from the data buss, depending on the state of the MWRITE signal.
Although everything has been done to ease construction and setting up, the kit is not recommended for the novice kit constructor due to the obvious complexity of the unit. Although a backup 'get-it-going' service is provided by the kit manufacturers in case of problems, would-be constructors in any doubt are advised to purchase the unit ready assembled and tested.
The double-width module consists of two main PCB assemblies, namely one analogue and one digital, onto which the front panel is attached, and between which a short multiway jumper ribbon cable runs. The digital PCB also carries a 'piggy-back' memory board which at present occupies an expansion socket. Memory expansion would then be affected either by replacing the memory board, or by extending the expansion connector to an expansion module.
Construction of the Digital Sampler/Delay module is, however greatly eased by the use of double sided PCBs, and since exclusive use is made of PC mounting connectors, switches and potentiometers, there is no interwiring to do. All the constructional notes should be carefully read and understood before you pick up the soldering iron. Also, since most of the ICs are MOS devices which are static sensitive, they should be left in their protective packaging until the PCB assemblies are ready for them.
The analogue board assembly should be tackled first. Looking at the screen printed component side, insert a track pin into each of the square pad positions, being careful not to miss any. The pins are best inserted while still in 'stick' form, breaking the stick away from the inserted leading pin each time. Solder the pins on both sides of the PCB. The PCB should then be populated according to the parts list, and the overlay printed on the PCB itself. Start with the lowest profile components first such as the diodes, gradually working up in height through resistors, IC sockets, transistors and capacitors to presets. Bending the leads of wire-ended components outward at 45 degrees prior to soldering will hold the components in place without running the risk of shorting together a pair of pads. Only insert ten or so components at a time to prevent crowding, soldering and cropping the leads at each stage. The ICs, pots, LEDs and switches should be left out until later. IC22 can however be soldered in at this point. Take great care when inserting any polarised components such as diodes and electrolytic capacitors to ensure they are orientated correctly. The buss connector and the five jack sockets can then be soldered whilst holding them firmly down onto the PCB. A piece of foam rubber laid on the bench comes in handy for holding connectors and the like in place on upturned PCBs during soldering.
Now insert one end of each of the two short ribbon cable jumpers into the component side of the PCB at the appropriate positions and solder. Fix the long spacer to the component side of the PCB using an M3 screw. Check the assembly so far very carefully, preferably with an eyeglass, being on the lookout for wrongly polarised components, dry joints and solder splashes. Once you are entirely happy with the assembly, carefully load the ICs, one at a time into their sockets. Some precautions should be taken to prevent static damage, although there's no need to be frightened of them; just make sure that that the devices are left in their protective packaging until the last moment. Touch both the conductive packaging and the component side foil on the PCB whilst transferring them, and avoid, if possible touching the the IC leads. It would be preferable not to wear a nylon sweater at the time, nor is it advisable to go for a walk around on a nylon carpet prior to the transfer!
Next month, we conclude construction with the assembly of the other two PCBs.
The Digital Sampler/Delay module is available from: Tantek, (Contact Details). The price inclusive of VAT and postage (within the UK) is £219.95 in kit form, or £299.95 ready assembled and tested. Further information on the modular rack system can be obtained from the above address, or by 'phoning (Contact Details).
Feature by Paul Williams
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