Digital Delay Line (Part 2)
Final part of our superb big value effects unit.
Part 2 concludes the project with full constructional details.
The complete circuit of the unit is shown in Figures 3 and 4, and operation may be clearer if the block diagram (Figure 2, published last month) is studied at the same time.
The input signal is amplified by the input amplifier IC21, to bring the signal up to a suitable operating level. Next the signal is filtered by two low pass filters, one of which has a 4kHz cut-off, and the other a 10kHz cut-off. The 4kHz or 10kHz operation is selected by S16. These are known as antialiasing filters; aliasing is an effect that sounds like ring modulation and is caused by harmonics of the input signal interacting with the analogue to digital conversion. If these harmonics are greater in frequency than ½ of the conversion frequency, then side bands will be generated that will fall within the audio spectrum: to prevent this from happening, the input signal is low-pass filtered to remove these high frequency harmonics.
The signal is then fed into the ADC (analogue to digital converter). This section continuously samples the analogue waveform, and measures the instantaneous amplitude which it describes with an 8-bit digital word. This word is then stored in the digital memory. In order to convert the analogue waveform into a digital word it must be 'frozen' long enough to allow the ADC to perform the measurement. The freezing is done with a sample and hold device, IC10. The 'lumpy' output of the sample and hold unit (TP8, see Figure 8) still represents the input signal; if it were low-pass filtered then the original waveform would be recovered, as in fact it is when it is reconstructed by the digital to analogue converter (DAC) after the selected time delay (TP10, Figure 8).
The ADC consists of three main sections, a comparator IC14, a successive approximation register (SAR) IC17, and a DAC IC13.
Their purpose in life is to measure the input voltage and to describe it with an 8-bit digital word. The SAR produces a binary code which it sends to the DAC; this generates an output voltage which the comparator compares with the input signal. The result of the comparison determines whether the MSB of the digital word is a 1 or a 0. The SAR then tests the next bit of the code, and then the next, until all 8 bits have been determined; the conversion is then complete. The 8-bit word causes the DAC to produce a voltage equal in magnitude to the input signal, therefore the word is a measurement of the input sample.
The DAC is in fact a companding DAC, and not a linear one; it can be operated in both compression and expansion modes. In the ADC (IC13) it compresses the signal, and in the DAC (IC33) it expands the signal thus giving an overall linear transfer function. The performance of the DAC and ADC can be described in several ways. First, the dynamic range: this is the ratio between the largest signal that the system can handle and the smallest. The dynamic range is 72dB which is quite good.
The signal to noise ratio is the ratio between the largest signal that the system can handle, and the output noise with no input signal. This may be better than 72dB, but it is not that important, because the system only generates digital noise (quantisation noise) when it is converting signals. The noise only appears when a signal output is being generated; this noise is related to the amplitude and spectrum of the input signal.
Now consider the signal to quantisation noise ratio. If the delay line is processing speech, then the quantisation noise is hardly noticeable; the noise is masked by the rapidly changing information in the speech. If the input signal is high in frequency compared to the selected bandwidth, then again the quantisation noise is lost, this time having been removed by the output filters. However, if the input signal is a low frequency pure tone then quantisation noise can be heard sizzling away in the background! This problem is overcome by giving the input signal a treble lift from 600Hz up to 6kHz (R3 and C3 give pre-emphasis) and by providing a treble cut at those same frequencies on the output signal (R86 and C31 give de-emphasis). The overall frequency response is flat, and the quantisation noise is selectively filtered out. The energy spectrum of most natural sounds falls off with increasing frequency, and so the pre-emphasis does not produce any signal overload problems.
The memory is 16K bytes long, being constructed from 2114L static RAMs (4 bits by 1K). The read/write cycle is as follows: the memory address is set up, and data is read from that memory location by being clocked into a latch (IC34) that drives the DAC (IC33). Next, data is written into the same memory location, the data being obtained from the ADC. The address is then incremented by one bit. If the full memory length were being used, then the address would have to count in a full circle (16K) to retrieve the data that had just been entered.
The output data is converted to an analogue voltage by the DAC (IC33). This voltage is quantised into steps, and it needs filtering to remove the unwanted harmonics that constitute these steps. Again a 4kHz and a 10kHz low pass filter (IC28,29,30,31) are used.
The master clock for the system is generated by a high frequency voltage controlled oscillator, IC1, 2 and 3. IC2 and 3 form a standard Schmitt trigger/integrator oscillator, the frequency of which is controlled by the current into pin 5 of IC3. IC1 is used as a buffer to drive the subsequent TTL stage.
IC8, 12 and 16 are binary dividers which generate the memory addresses A0 to A18. A0 to A4 are used to generate timing signals, such as read, write, start conversion, sample, and A5 to A18 are used as the memory address. Shorter time delays are obtained by using smaller sections of the memory, by progressively disabling the memory addresses using IC15, 18 and 10. The memory is sectioned into four quarters (see memory options in parts list) and so the top four time delay selections have equal time increments, but the lower eight selections provide time delays in octave increments. The master clock oscillator frequency may be manually controlled by RV3, or modulated by the low frequency triangle oscillator IC26, 27.
The timing diagram for one conversion read/write cycle is shown in Figure 5. All the waveforms will be clearly visible at the indicated test points (TP1-12). The memory reset timing is shown in Figure 6. A18 has a period of 1.6 seconds or 0.64 seconds, depending on the selected bandwidth. The reset pulse has a period of less than one micro-second, so don't be surprised if you cannot see it! Figure 7 shows the memory column select decoding. The number of columns selected will depend on the time delay selected by SW12, 13, 14, 15.
Most of the components, including controls, are mounted on one large double sided PCB, whilst two smaller single sided boards carry the time delay selector switches and the power supply components (with the exception of the transformer). Powertran's PCBs will not carry a printed component legend, but all the component positions are identified in Figures 9, 10 and 11 and construction should be straightforward. Before mounting any components on the large PCB, the tracks on the top of the board should be linked through with pins (special through-pins are supplied in the kit) and soldered top and bottom. Sockets are recommended for the ICs, and again, these are provided in the kit. As always, take special care with the soldering, and check for dry joints, solder splashes and correct component orientation before switching on.
There is very little wiring to be done. The switch board is linked to the main board with two lengths of ribbon cable, as shown on the component overlays; the PSU board and transformer wiring is shown in Figure 12. The connections to the freeze switch and footswitch socket are on the switch board diagram.
If required, the delay unit may be built with ¼, ½ or ¾ memory to begin with, and this is simply a matter of omitting some of the components: the parts list gives details.
Once all the soldering is done, do not insert any ICs except those in the power supply. Power up and test the regulated supply rails (the unregulated rail voltages only refer to a fully loaded power supply). Insert the ICs, in lots of 10, and then power up and check the regulated supply rails. Do this until all the ICs are inserted. Don't forget to turn off the power when you are putting them in! Having completed a successful power up you can now test the unit.
Connect a signal and check all is functional. If not, then check to see if all the TP waveforms are being generated correctly. Also look at all 19 address lines. If you experience a regular repeating fault in the memory section then you may have a nonfunctional area of memory. Check out the address lines, the data bus and the column decoding. If these are all OK then it is probable that a memory chip is faulty. This can be located by a process of substitution. Finally, set up the presets as follows:
1) Set up the unit for a long echo, and set REPEAT to maximum. Adjust RV8 so that repeats continue for a long time, but not so that they grow in amplitude.
2) Measure the voltage on the positive end of D1; it should be +4.7V. Monitor IC27 pin 1, and adjust RV9 so that the triangle waveform is offset so that its bottom point is at +4.7V. If you don't have a 'scope, a voltmeter may be used, but turn down the sweep speed to avoid misleading readings.
3) Turn the time delay pot anti-clockwise, and select manual control of time delay. Select 10kHz bandwidth, and measure the frequency at test point 3 (TP3). Adjust RV10 so that the frequency is about 40kHz. Now select 4kHz bandwidth, and adjust RV11 so that the frequency is about 160kHz. These frequencies can be set without instruments by entering a short signal, freezing it and setting the pre sets so that the delay times on the longest setting are 0.64 secs and 1.6 secs (time 10 repeats, i.e. 6.4 secs and 16 secs).
4) The sample and hold offset adjustment RV12 only produces a small DC shift, which when compared to the 10Vp-p audio signal level at this point is not significant. However, if the ADC is dithering between two quantised states (and hence producing 1 LSB of dithering noise) then the DC offset can be used to shift the analogue voltage by just enough to prevent this. Listen to the delayed output, and adjust RV12 for minimum noise. Find the best pre-set position by manually adjusting the delay time. The delay effects unit is now ready for use.
The E&MM Digital Delay Line is obtainable as a complete kit of parts from Powertran Electronics, (Contact Details). With ¼ memory, ie 400ms maximum delay, the kit costs £130 + VAT. Extra memory parts are £9.50 + VAT per 400ms, so the full 1.6s delay would cost £158.50 + VAT.