The Programmable Digital Sound Generator (Part 3)
Part 3: The Detailed Program Interface
Our analysis of the Programmable Digital Sound Generator enters its third phase. Your guide: Alan Boothman.
Designer Alan Boothman takes a look at the interface section of this new add-on music system for home computers, paying particular attention to address locations.
In order to control the PDSG, a single page of address locations is required within the memory map of the host computer. The board is configured to match the extended page concept of the BBC Model B computer, and is initialised by writing &70 (112 in decimal) to address &FCFF, which sets a latch until a Reset operation occurs. All further addressing is then carried out using page &FD, ie. locations &FD00 to FDFF. Details are given later on how to disable this part of the system to interface with other computers.
Within the chosen page, addresses 0-127 are reused four times in order to allow Music Load (0-127), Waveform Load (0-127), Low Auxiliary (Keyboard) Read (0-31), and High Auxiliary Read or Write (0-15). Addresses above 127 are reserved to set the Control Register mode, which defines which of the above is active, and includes on/off control of sound and interrupt operation. Addresses 129-255 are not normally used.
The Control Register is set up by writing to address 128 using the data shown in Figure 1. On powering-up, or after a computer Reset, the register is set to zero, thus disabling the sound output and interrupt generator. One or both of these may then be enabled, together with one of the four PDSG functions, by writing the sum of the required activities to address 128. Only one PDSG function should be selected at a particular time: the others are automatically deactivated by the zeros in their bit positions.
Music loading involves the writing of data to the registers shown in Figure 2, which cover Level, Waveform, Channel, and Frequency as required for each logical oscillator. In order to change an oscillator parameter during normal operation, when both sound and interrupt are required, writing 7 to address 128 sets the Control Register, after which data corresponding to the new value is written to the relevant address (0-127) from Figure 2. The Control Register will remain set in Music Load mode until a further write operation takes place to address 128.
Level data is a number between 0 and 255, which gives a linear increase in amplitude. Waveform and Channel are combined into a single number. For the normal configuration of two 2Kx8 memories, the 128 Byte tables in memory 1 have base numbers of 0-15 (31), and 32-47 (63) in memory 2. The figures in brackets indicate the corresponding numbers if 4Kx8 EPROMs are used in either position.
The channel positions are defined as Left 64, Right 128, and Centre 192. Consequently, in order to select the first waveform in memory 2 and the right-hand sound channel, a value of 160 (32+128) is written to the address of the required oscillator. Figure 3 summarises the relevant data to obtain this information for the required combination. Two bytes are required to define frequency and a suitable formula will be given later.
Waveforms are loaded in 128 byte single-table streams. The Control Register is first set to Low Auxiliary by writing 8 (9, 10 or 11) to address 128, and the waveform table base number is then written to address zero. The Control Register is next set to waveform transfer by writing 32 (33, 34 or 35) to address 128. The stream of table data is then written to address 0 to 127 in the PDSG. A routine can be used to load a waveform set by repeating all the above steps for each table.
For programming, the bus is split into two parts, and although the Low Auxiliary Control position was used in the write mode to direct waveform table transfer, the Low Auxiliary bus is actually read only. 32 addresses (0-31) are available on the eight-bit bus, which allows reading of up to 256 switches with suitable decoding. The 61-note keyboard adopted has two pole switches, using bit 4 of the address to define which pole is being scanned. Addresses 0 to 7 therefore scan the up position of the eight blocks of keys, with the top key (number 61 on the keyboard) being treated as number 63 in the scan, and the footswitches as numbers 1 and 2; addresses 16 to 23 scan the corresponding down position of the key blocks. Addresses 8 to 15 and 24 to 31 may be used for additional input devices, but in hardware terms, it should be noted that bit 4 is actually inverted. To scan the keyboard the Control Register is set to Low Auxiliary by writing 8 (9, 10 or 11) to address 128 and then reading from the required address between 0 and 31.
Unless High Auxiliary is selected in the Control Register, bit 5 of the bus remains at level 0 and is used as a device select level, ie. high for peripheral devices (other than the keyboard) which may be connected to the bus. In High Auxiliary mode, bit 4 should always be fed with zero from the software, and in the bus it will appear as a negative Write Enable pulse. The High Auxiliary bus is operated by writing 16 (17, 18 or 19) to address 128 and then reading or writing addresses 0-15.
Feature by Alan Boothman
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